| FCS_CRC_EN | For SPI1 initialize crc32 module before writing encrypted data to flash. Active low. |
| TX_CRC_EN | For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable |
| WAIT_FLASH_IDLE_EN | wait flash idle when program flash or erase flash. 1: enable 0: disable. |
| FASTRD_MODE | This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable. |
| FREAD_DUAL | In the read operations read-data phase apply 2 signals. 1: enable 0: disable. |
| RESANDRES | The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable. |
| FREAD_QUAD | In the read operations read-data phase apply 4 signals. 1: enable 0: disable. |
| WP | Write protect signal output when SPI is idle. 1: output high 0: output low. |
| WRSR_2B | two bytes data will be written to status register when it is set. 1: enable 0: disable. |
| FREAD_DIO | In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. |
| FREAD_QIO | In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. |
| RD_BIT_ORDER | In read-data (MISO) phase 1: LSB first 0: MSB first |
| WR_BIT_ORDER | In command address write-data (MOSI) phases 1: LSB firs 0: MSB first |